Principal Engineer_PDK Design Enablement And Design Services

ABOUT THE COMPANY:

Tata Electronics Private Limited (TEPL) is a greenfield venture of the Tata Group with expertise in manufacturing precision components.

Tata Electronics (a wholly owned subsidiary of Tata Sons Pvt. Ltd.) is building India’s first AI-enabled state-of-the-art Semiconductor Foundry. This facility will produce chips for applications such as power management IC, display drivers, microcontrollers (MCU) and high-performance computing logic, addressing the growing demand in markets such as automotive, computing and data storage, wireless communications and artificial intelligence.

Tata Electronics is a subsidiary of the Tata group. The Tata Group operates in more than 100 countries across six continents, with the mission 'To improve the quality of life of the communities we serve globally, through long term stakeholder value creation based on leadership with Trust.’

Job Description:

We are looking for a skilled and motivated pCell Development Engineer with 4+ years of experience to design, develop, and maintain parameterized cells (pCells) for advanced analog and mixed-signal (AMS) technologies. This role involves building scalable and reusable layout automation solutions, enabling design productivity, and ensuring high-quality layout generation in collaboration with circuit and layout teams.

The ideal candidate will have strong expertise in pCell development from scratch, technology file customization, and feature enablement using SKILL, with additional exposure to pCell methodologies being an advantage.

Responsibilities:

• Develop complex pCells from scratch using SKILL for analog and mixed-signal devices and structures.
• Enhance and maintain existing pCell libraries, ensuring robustness, scalability, and usability across design teams.
• Perform and manage Techfile updates, including layer definitions, rules, display resources, and process-specific configurations.
• Implement advanced layout features such as: Device abutment, Folding/multiplexing support, Modgen (parameterized array/matrix) enablement
• Enable new device development from scratch, aligning with process design kits (PDKs) and foundry requirements.
• Collaborate closely with layout designers and circuit engineers to understand requirements and improve usability of pCells.
• Support integration of pCells within AMS design flows and ensure compatibility with EDA tools such as Cadence Virtuoso.
• Debug and resolve issues related to pCell behavior, layout generation, and design rule compliance.
• Ensure pCells meet DRC/LVS requirements and are compliant with physical verification flows.
• Collaborate with CAD and methodology teams for flow alignment and automation improvements.
• Contribute to documentation, guidelines, and best practices for pCell development and usage.
• Evaluate and explore new automation approaches, including pCell frameworks and emerging layout generation techniques.
  
  

• Strong expertise in Cadence SKILL programming for pCell development.
• Deep understanding of: Analog and mixed-signal layout methodologies, Device construction and matching techniques
• Hands-on experience with: Techfile customization and maintenance of Layout verification flows (DRC, LVS)
• Experience in implementing advanced pCell features such as: Abutment handling, Folding techniques and Modgen enablement
• Familiarity with Cadence Virtuoso layout environment and design flows.
• Strong debugging and problem-solving skills for layout and pCell-related issues.
• Good understanding of PDK development concepts.
• Proficiency in scripting languages (Python/Shell/TCL) is a plus for workflow automation.
• Strong communication and collaboration skills.
  
  

• B.Tech / M.Tech in Electronics, Electrical Engineering, Microelectronics, or a related field.
  
  

• 4+ years of experience in pCell development and layout automation.
• Proven experience in developing pCells from scratch using SKILL.
• Exposure to pCell development frameworks is an added advantage.
• Experience with multiple technology nodes (e.g., 180nm to 28nm or below).
• Familiarity with device structures (RF, high-voltage, or MOSFET based layouts).
• Knowledge of DFM, yield optimization, and layout reliability techniques.
• Exposure to automation and emerging trends (e.g., ML-assisted layout generation).