Principal ASIC Physical Design Engineer

Job Title:

• Principal ASIC Physical Design Engineer
  
  

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You are the person teams turn to when timing closure looks impossible and the clock tree feels like a puzzle with missing pieces. You know the difference between a design that passes signoff and one that ships with margin to spare, because you have spent years making those calls at 7nm and below. You do not just push buttons in ICC2 or PrimeTime—you know why a constraint matters, and you catch issues before they ripple downstream. When someone asks about integrating a tricky mixed-signal macro, you have a mental toolkit of what can go wrong and how to make it work. You thrive on the hard problems: GHz-level timing, power optimization, and the reality of silicon bring-up. You want your work to show up in real products, not just in a tapeout report. Sharing what you know is second nature—mentoring junior engineers, reviewing a teammate’s floorplan, or explaining a tradeoff to a colleague in the US. You care about getting the details right, but you do not get stuck in them. You move projects forward, ask the right questions, and always look for a better way to do things.

What Youll Be Doing

• Implement and integrate Physical Design for ASICs at advanced nodes (10nm, 7nm, 6nm and below) using tools like Synopsys ICC2, PrimeTime, and StarRC.
• Drive timing closure for high-frequency designs above 4GHz, handling constraint management, analysis, and optimization.
• Work hands-on with clock tree synthesis, skew balancing, and robust clock distribution for complex SoCs and IPs.
• Collaborate closely with teams in Bangalore and the US, joining technical discussions, design reviews, and troubleshooting sessions.
• Integrate mixed-signal hard macro IPs, solving unique interface and floorplan challenges as they arise.
• Mentor junior engineers, sharing best practices and elevating the team’s technical capability.
• Develop and optimize automation scripts in Tcl, Perl, or Python to streamline physical design flows and improve productivity.
• Support and improve methodologies for floorplanning, placement, routing, and power optimization.
  
  

The Impact You Will Have

• Deliver HPC Controller IPs that will power the next wave of consumer and enterprise devices.
• Push Synopsys’ reputation for silicon-proven, high-performance IP at the most advanced process nodes.
• Raise the bar for quality and innovation in timing closure, clock tree synthesis, and mixed-signal integration.
• Help global teams align and execute, ensuring projects hit milestones and customers get what they need, on time.
• Enable faster, more robust tapeouts by improving design flows and mentoring the next generation of engineers.
• Influence product differentiation through hands-on technical contributions and creative problem solving.
• Shorten time-to-market for customers by anticipating and solving critical design challenges early.
  
  

What Youll Need

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or related field.
• 10+ years of hands-on experience in ASIC physical design at 10nm, 7nm, 6nm or below.
• Deep proficiency with Synopsys ICC2, PrimeTime, StarRC, and similar industry tools.
• Demonstrated success in timing closure for high-frequency designs (4GHz and above), including constraint management and analysis.
• Practical experience integrating HPC Controller interface IPs and mixed-signal macros.
• Solid knowledge of scripting (Tcl, Perl, Python) for automating physical design tasks.
• Strong skills in debugging complex design and integration issues.
  
  

Who You Are

• You explain why a timing violation matters, not just how to fix it, and adapt your message for a peer or a VP.
• When a design review gets stuck, you break down the complexity and help the team move forward.
• You spot risk early and act, rather than waiting for issues to escalate.
• Sharing knowledge is second nature—you mentor, document, and help others level up.
• You keep an eye on quality, even under pressure, and push for continuous improvement in tools and process.
• You are comfortable switching context between deep technical work and cross-site collaboration, always keeping the larger goal in view.
  
  

The Team Youll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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