PD Lead- ODC

Job Requirements

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

A Senior/Tech architect (Physical Design) with 15+ years’ experience and EDA tools expertise (Synopsys/Cadence) to lead complex SOC implementation from synthesis to GDSII is required. Primary responsibilities will be to manage advanced nodes (4nm/2nm) SOC/Sub-system implementation, realizing PPA (Power, Performance, Area) goals, collaborating with cross-functional teams, tweaking design methodology and mentoring junior engineers..

Key Responsibilities

• Technical Leadership: Lead complex SoC/sub system physical design implementation from Synthesis to tape-out.
• Advanced Floorplanning: Lead hierarchical floo rplanning, tCIC cleanup, and pin placement for SOC/sub-system
• PPA Optimization: Optimize design for maximum performance, minimum power, and smallest area using advanced methodologies.
• Sign-off: Lead top-level static timing analysis (STA), EM/IR analysis, and physical verification (DRC/LVS/ERC).
• Methodology & Automation: Enhance/Tweak backend design flows, scripts (Tcl/Perl) using AI to automate and improve efficiency.
• Mentorship: Mentor senior and junior staff members, providing technical guidance and design reviews.
• Collaboration: Coordinate with RTL and DFT teams to address architectural issues.
  
  

Required Qualifications

• Experience: 15–20+ years of experience in VLSI physical design.
• Education: B.Tech/M.Tech in Electrical/Electronics Engineering.
• Process Nodes: Extensive experience with advanced technology nodes (4nm, 2nm).
• Tool Proficiency: Expertise in Synopsys Fusion Compiler or Cadence Innovus.
• Scripting: Proficiency in Tcl, and Perl, to manage automation with AI
• Expertise: Deep understanding of clock tree synthesis (CTS), timing closure, and low-power techniques.
  
  

Core Competencies

• Strong leadership, communication, and project management skills.
• Track record of leading teams to first pass Silicon success consistently

We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.

We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.

Work Experience

• Experience: 15–20+ years of experience in VLSI physical design.
• Education: B.Tech/M.Tech in Electrical/Electronics Engineering.
• Process Nodes: Extensive experience with advanced technology nodes (4nm, 2nm).
• Tool Proficiency: Expertise in Synopsys Fusion Compiler or Cadence Innovus.
• Scripting: Proficiency in Tcl, and Perl, to manage automation with AI
• Expertise: Deep understanding of clock tree synthesis (CTS), timing closure, and low-power techniques.
• Strong leadership, communication, and project management skills.
• Track record of leading teams to first pass Silicon success consistently

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