Lead RTL Design Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and highly experienced ASIC Digital Design engineer, eager to push the boundaries of high-performance silicon IP. With a deep understanding of digital design principles, you thrive in complex technical environments and relish the challenge of architecting and implementing world-class solutions. You possess a strong background in RTL design, synthesis, and verification, and are comfortable collaborating across multidisciplinary teams to deliver robust, scalable, and innovative products. Your problem-solving skills are matched by your attention to detail, and you are driven by a commitment to quality and technical excellence. You excel at taking technical ownership, providing mentorship, and ensuring the seamless transition from specification through tape-out. As a leader, you foster a culture of continuous learning, inclusivity, and creative thinking, empowering your peers and advancing the team’s collective success. You are motivated by working on cutting-edge IPs such as UCIe, DDR, and Die-to-Die interfaces, and you stay current with industry trends and emerging technologies, including AI/ML. Your communication skills enable you to clearly articulate technical concepts and collaborate effectively with stakeholders, and your passion for innovation inspires those around you.

What You’ll Be Doing:

• Leading RTL design and implementation for high-performance mixed signal IPs including UCIe, DDR, and Die-to-Die interfaces
• Taking technical ownership of assigned blocks, developing architecture and microarchitecture, and driving design reviews
• Specifying, architecting, and implementing digital logic using Verilog/SystemVerilog
• Collaborating with circuit design, verification, physical design, and validation teams to ensure design closure and integration
• Driving logic synthesis, lint, clock domain crossing (CDC), design-for-test (DFT), and timing closure for your blocks
• Analyzing coverage, debugging functional and timing issues, supporting integration, and authoring technical documentation
• Supporting silicon bring-up and participating in tape-out activities as required
  
  

The Impact You Will Have:

• Accelerate the development of industry-leading mixed signal IPs, enabling next-generation connectivity and performance
• Contribute to Synopsys’ reputation as a leader in advanced semiconductor design solutions
• Drive innovation in digital design and architecture, influencing key product features and capabilities
• Ensure the delivery of high-quality, reliable, and scalable IPs that meet stringent market requirements
• Mentor and guide junior engineers, fostering a collaborative and inclusive team environment
• Help Synopsys maintain its competitive advantage by integrating emerging technologies such as AI/ML into design processes
  
  

What You’ll Need:

• B.E./M.E. in Electrical/Computer Engineering or equivalent
• 8+ years of experience in RTL design for IP, ASIC, or SoC
• Expertise in Verilog/SystemVerilog RTL coding, synthesis, CDC, and DFT concepts
• Strong familiarity with timing analysis, static timing analysis (STA), and EDA flows (synthesis, lint, CDC, etc.)
• Exceptional debug skills and ability to resolve functional and timing issues
• Experience with scripting languages such as Python, TCL, or Perl
• Understanding of standard protocols like AMBA, PCIe/UCIe, DDR is highly desirable
• Participation in tape-outs and silicon bring-up processes
• AI/ML knowledge is a plus
  
  

Who You Are:

• Innovative thinker with a growth mindset and a passion for continuous learning
• Strong communicator, able to articulate complex ideas clearly to both technical and non-technical audiences
• Team player who thrives in collaborative, cross-functional environments
• Detail-oriented, organized, and able to manage multiple priorities effectively
• Resilient problem solver who approaches challenges with creativity and perseverance
• Inclusive leader who values diversity and empowers others
  
  

The Team You’ll Be A Part Of:

You’ll join a dynamic, high-performing engineering team at Synopsys Bangalore, focused on designing and delivering advanced mixed signal IPs for leading-edge semiconductor applications. The team prides itself on technical excellence, collaboration, and innovation, working closely with global counterparts across design, verification, and product engineering. Together, you’ll drive the creation of IPs that power tomorrow’s connectivity and computing solutions.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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