Functional Verification Engineer

Project Role : Functional Verification Engineer

Project Role Description : Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out.

Must have skills : SoC Verification

Good to have skills : NA

Minimum 5 Year(s) Of Experience Is Required

Educational Qualification : 15 years full time education

Summary:

Total Industry Experience Minimum 7 years in hardware verification/validation roles DDR Protocol Experience 5+ years hands-on DDR4 and/or DDR5 verification & validation Memory Subsystem Experience Strong familiarity with DRAM architecture, timing, and signal integrity Bring-up Experience Experience with silicon/board bring-up and post-silicon debug Prior DDR Generations DDR3 / LPDDR background advantageous but not essential

As a Functional Verification Engineer, a typical day involves developing and implementing comprehensive testbenches to ensure the functional accuracy of digital designs at both block and system levels. The role requires creating various types of tests, including constrained-random, directed, and coverage-driven, to thoroughly validate design functionality. Collaboration with design and architecture teams is essential to identify potential corner cases and guarantee exhaustive functional coverage prior to tape-out. This position demands a proactive approach to problem-solving and continuous communication across teams to maintain high-quality verification standards throughout the project lifecycle.

Roles & Responsibilities:

• Develop and execute DDR4/DDR5 verification plans covering functional, performance, and compliance testing
• Build and maintain UVM-based testbenches for DDR PHY and memory controller IP verification
• Lead post-silicon DDR bring-up, characterisation, and margin analysis activities
• Perform signal integrity analysis and correlate simulation results with lab measurements
• Drive JEDEC DDR4/DDR5 compliance testing and liaise with memory vendors
• Develop automated regression suites and analyse results to identify coverage gaps
• Debug and root-cause DDR failures across simulation, emulation, and silicon environments
• Collaborate with RTL designers to resolve protocol violations and timing issues
• Produce detailed technical reports, test plans, and sign-off documentation
• Provide technical mentorship to junior verification engineers
  
  
  

• Deep understanding of DDR4 (JEDEC JESD79-4) and DDR5 (JESD79-5) specifications
• Knowledge of DDR5 RCD (Registering Clock Driver), SPD Hub, and on-die ECC
• Familiarity with signal integrity concepts: eye diagrams, jitter, crosstalk, and impedance
• Understanding of DDR training algorithms: read/write levelling, ZQ calibration, ODT tuning
• Experience with LPDDR4/5 desirable
  
  
  

• Proficient in UVM (Universal Verification Methodology) for DDR PHY/Controller verification
• Experience writing SystemVerilog testbenches and functional coverage models
• Familiarity with formal verification methods and assertion-based verification (SVA)
• Simulation tool experience: Synopsys VCS, Cadence Xcelium, Mentor Questa
• Regression management and debug using waveform tools (Verdi, DVE, SimVision)
  
  
  

• Post-silicon validation experience including BIOS/firmware-level DDR bring-up
• Use of lab equipment: oscilloscopes, protocol analysers (e.g. Teledyne LeCroy DDR), logic analysers
• Experience with JEDEC compliance testing and margin analysis
• Memory stress testing and reliability validation (e.g. memtest, custom stress patterns)
• Root cause analysis for DDR-related failures: timing violations, data integrity issues
  
  
  

• Scripting in Python, Perl, or TCL for test automation and results analysis
• Familiarity with version control systems: Git, Perforce
• Experience with EDA tools: Synopsys VC Verification, Cadence Incisive
• SPICE simulation exposure for signal integrity analysis desirable
  
  
  

• BEng / MEng in Electrical Engineering, Computer Engineering, or Electronics Essential Or equivalent demonstrated experience
• MSc in VLSI / Embedded Systems / Microelectronics Desirable Advantageous for senior roles
• JEDEC Membership / Standards Familiarity Desirable DDR4/DDR5 spec knowledge required
• Synopsys / Cadence Tool Certification Desirable Vendor-specific