Formal Verification Engineer

Project Role : Formal Verification Engineer

Project Role Description : Ensure design correctness using mathematical methods like model checking and equivalence checking, without relying on simulation. Detect corner-case bugs early in the design cycle to improve quality and reduce verification time.

Must have skills : SoC Verification

Good to have skills : NA

Minimum 3 Year(s) Of Experience Is Required

Educational Qualification : 15 years full time education

Summary:

As a Formal Verification Engineer, you will ensure design correctness using mathematical methods such as model checking and equivalence checking. Your typical day will involve analyzing design specifications, developing formal models, and applying verification techniques to detect corner-case bugs early in the design cycle. This proactive approach will significantly enhance the quality of the designs and reduce the overall verification time, allowing for a more efficient development process.

Roles & Responsibilities:

• Expected to perform independently and become an SME.
• Required active participation/contribution in team discussions.
• Contribute in providing solutions to work related problems.
• Collaborate with cross-functional teams to gather requirements and provide feedback on design specifications.
• Develop and maintain formal verification environments to ensure comprehensive coverage of design scenarios.
  
  
  

• Must To Have Skills: Proficiency in SoC Verification.
• Strong understanding of formal verification techniques and tools.
• Experience with model checking and equivalence checking methodologies.
• Familiarity with hardware description languages such as Verilog or VHDL.
• Ability to analyze complex designs and identify potential verification issues.
  
  
  

• The candidate should have minimum 3 years of experience in SoC Verification.
• This position is based at our Bengaluru office.
• A 15 years full time education is required.