Digital RTL Frontend Designer HPM48ST RM 4138

Position: Digital RTL Frontend Designer (HPM48ST RM 4138)

Role Overview

We are seeking a talented Digital RTL Frontend Designer with 4–8 years of experience in CPU/bus/peripheral integration OR DSP/custom dataflow design OR IP integration and NoC configuration. The role involves architecting and implementing RTL designs for complex SoCs, ensuring performance, scalability, and testability.

Key Responsibilities

• CPU/BUS/Peripheral Integration: Integrate CPU cores, system buses, and peripheral subsystems into digital designs.
• DSP/Custom Dataflow: Design and optimize DSP blocks and custom dataflow architectures for high-performance applications.
• IP Integration: Incorporate third-party and proprietary IPs into SoC designs, ensuring seamless functionality.
• NoC Configuration: Configure and validate Network-on-Chip interconnects for scalable system architectures.
• DFT Implementation: Apply design-for-test methodologies (scan insertion, BIST, boundary scan) to improve testability and reliability.
• Collaborate with backend teams for synthesis, timing closure, and verification.
• Maintain and enhance design documentation to reflect architectural and functional updates.
  
  

• Strong proficiency in RTL design (Verilog/VHDL/SystemVerilog).
• Hands-on experience with CPU, bus, and peripheral integration.
• Knowledge of DSP architectures and custom dataflow design.
• Experience in IP integration and NoC configuration.
• Familiarity with DFT techniques and methodologies.
• Exposure to FPGA/ASIC design flows including synthesis, timing, and verification.
• Strong debugging and problem-solving skills in simulation and lab environments.
  
  

• Strong analytical and architectural thinking.
• Ability to work independently and in cross-functional teams.
• Excellent communication and documentation skills.