Design Verification Engineer - IP

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Design Verification Engineer - IP

Job Summary

We are seeking a Senior Design Verification Engineer (IP DV) to verify complex, reusable High‑Performance Computing (HPC) IP blocks used across multiple SoC programs. The role requires strong ownership of IP‑level verification, deep understanding of protocols and micro‑architecture, and the ability to build scalable, reusable verification environments that support integration into larger SoCs.

The role also emphasizes adoption of AI‑assisted verification techniques to improve debug productivity, regression efficiency, and verification quality for performance‑critical IPs.

The ideal candidate is hands‑on, detail‑oriented, and comfortable working closely with IP design and architecture teams to deliver high‑quality, production‑ready IPs.

Key Responsibilities

• Own IP‑level functional verification from specification review to sign‑off for HPC‑class IPs
• Develop comprehensive IP verification plans, including corner cases, stress, and error scenarios
• Build reusable SystemVerilog / UVM‑based verification environments for performance‑critical IPs
• Develop UVM agents, sequences, scoreboards, and coverage models aligned with IP reuse goals
• Create directed and constrained‑random tests targeting IP functionality, configuration space, and protocol compliance
• Drive functional, code, and assertion coverage closure at IP level
• Verify multiple configurations, modes, and parameterizations, including high‑throughput and concurrency scenarios
• Perform detailed debug of RTL and testbench issues, working closely with IP designers
• Leverage AI‑assisted verification techniques (e.g., log analysis, regression triage, debug acceleration, coverage insights) to improve verification efficiency
• Ensure verification collateral is clean, reusable, and well‑documented for downstream SoC teams
• Review IP specifications, micro‑architecture documents, and RTL for verification completeness
• Support IP release, handoff, and integration by SoC verification teams
• Mentor junior DV engineers and promote best practices, including adoption of productivity‑enhancing AI tools
  
  
  

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or related field
• 4–6 years of hands‑on Design Verification experience, primarily at IP level
• Strong expertise in SystemVerilog and UVM methodology
• Solid understanding of digital design and micro‑architecture concepts
• Proven experience with assertion‑based verification (SVA)
• Strong knowledge of functional and code coverage techniques
• Experience verifying configurable, reusable, HPC‑class IPs
• Strong debug skills using industry simulators (VCS, Xcelium, Questa, etc.)
  
  
  

• Experience verifying HPC or performance‑critical IPs (data paths, fabrics, accelerators, memory or interconnect IPs)
• Experience verifying standard IP protocols such as:
• AMBA (AXI, AHB, APB, ACE)
• PCIe, USB, DDR, or interconnect fabrics
• Exposure to AI‑based / ML‑assisted verification tools or flows, such as:
• AI‑assisted log analysis and failure triage
• Intelligent regression analysis or coverage gap identification
• Debug productivity tools leveraging data analytics or pattern recognition
• Experience with parameterized IPs and multiple operating modes
• Knowledge of low‑power features (clock gating, power states, UPF/CPF)
• Exposure to formal verification at IP level
• Scripting skills in Python, Perl, or Shell for regression, automation, and AI‑assisted workflows
• Experience delivering IPs used across multiple SoC programs
  
  

• Strong sense of ownership and accountability
• Ability to work independently on complex, performance‑sensitive IPs
• Clear communication with design, architecture, and SoC teams
• Mentoring mindset and collaborative attitude
  
  
  

• Opportunity to work on cutting‑edge silicon products
• High ownership and technical growth
• Collaborative and learning‑oriented engineering culture
• Competitive compensation and benefits