Analog Layout Staff Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements of their target applications, and get differentiated products to market quickly with reduced risk. We are hiring leaders for our next generation DDR/HBM PHY IPs!

You Are:

You are a driven and passionate engineer with a strong foundation in CMOS, FinFET, and GAA process technologies at 7nm and below. You thrive in a collaborative environment, leveraging your technical expertise and leadership to drive innovative solutions in layout design. With a minimum of 5 years of relevant experience, you bring hands-on proficiency in layout development and a keen eye for detail, ensuring the highest quality standards are met. You are adept at mentoring and guiding junior engineers, fostering an inclusive and growth-oriented team culture. Your experience spans floorplanning, layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, and IO frame requirements. You excel in cross-functional settings, bridging gaps across teams, and facilitating effective communication and project execution. Your understanding of PHY level customer requirements enables you to deliver differentiated products that meet demanding timelines and technical specifications. You are committed to continuous learning, adapting to evolving technologies, and championing diversity and inclusion within your team. Your exceptional written and verbal skills empower you to articulate complex ideas clearly and engage stakeholders at all levels. If you share our commitment to innovation and excellence, you’ll find a rewarding career and a welcoming community at Synopsys.

What You’ll Be Doing:

• Leading the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies.
• Hands-on execution of layout development, ensuring precision and adherence to industry standards.
• Mentoring and supporting junior engineers, fostering technical growth and knowledge sharing within the team.
• Estimating project efforts, planning schedules, and executing projects in cross-functional settings.
• Collaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks.
• Managing the release process, ensuring timely delivery and consistent quality of layout deliverables.
  
  

The Impact You Will Have:

• Accelerate the integration of advanced silicon IP into customer SoCs, enabling faster time-to-market.
• Drive innovation in DDR/HBM PHY IP, contributing to Synopsys’ leadership in semiconductor technology.
• Enhance product quality and reliability through rigorous layout reviews and quality assurance processes.
• Mentor and empower the next generation of engineers, fostering a culture of excellence and inclusion.
• Collaborate across functions to deliver differentiated products that meet unique customer requirements.
• Influence the development of efficient, scalable layout solutions for emerging process technologies.
  
  

What You’ll Need:

• BTech/MTech degree in Electrical Engineering, Electronics, or related field.
• 5+ years of relevant experience in layout design for CMOS, FinFET, GAA process technologies (7nm and below).
• Expertise in layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements.
• Strong understanding of floorplan techniques and deep submicron effects.
• Proven ability to lead projects and deliver best product quality within tight timelines.
  
  

Who You Are:

• Collaborative and team-oriented, with a commitment to inclusion and diversity.
• Detail-oriented, with strong problem-solving and analytical skills.
• Effective communicator, both written and verbal, with excellent interpersonal abilities.
• Adaptable and eager to learn, embracing new technologies and methodologies.
• Empathetic mentor, fostering accountability, ownership, and technical growth in others.
  
  

The Team You’ll Be A Part Of:

You will join a highly skilled and diverse team of engineers focused on developing next-generation DDR/HBM PHY IPs. The team is driven by innovation, collaboration, and technical excellence, working together to deliver world-class silicon IP solutions that power the Era of Smart Everything. You’ll be part of a supportive environment that values individual contributions and collective success.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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